1. Field of the Invention
The present invention relates to integrated circuit (IC) devices, and in particular, to floating capacitive structures on an IC chip.
2. Discussion of the Related Art
In a mixed-mode, analog-and-digital integrated circuit (IC), a voltage-independent, or "floating" capacitor is a commonly required component. Such a capacitor must maintain a constant capacitance over a range of terminal voltage signals. A floating capacitor can be created in a number of ways. For example, a floating capacitor can be formed by providing a dielectric layer between two polysilicon layers or two thin film metal layers. Alternatively, a capacitive structure could be manufactured by providing a conductive layer beneath the gate oxide of a typical CMOS device. However, all these structures require steps additional to a conventional CMOS process. Any such additional steps beyond the basic CMOS manufacturing sequence add time, complexity, and cost to the final chip.
In U.S. Pat. No. 4,786,828, issued Nov. 22, 1988 to Hoffman, a floating capacitor is described which can be manufactured using conventional CMOS process steps. As shown in FIG. 1, FET devices 102 and 103 are connected in series at their gate terminals. The source, drain and body terminals of each device are combined to create a single signal terminal on each device. A biasing network, made up of series-connected FET devices 106, 107, 108, and biasing FET device 105, is applied to the gate terminals of FET devices 102 and 103. Device 105 provides the necessary output voltage to keep devices 102 and 103 operating in their saturation regions. While the invention of Hoffman can be implemented with conventional CMOS process, capacitive performance problems can develop.
Due to the physics of semiconductor devices, a small parasitic capacitance exists at the substrate junction in CMOS structures. Because Hoffman commonly connects source, drain, and body terminals of each of FET devices 102 and 103, and uses these common connected terminals as the signal terminals of capacitive circuit 101, parasitic capacitances C204 and C205 are created as shown in FIG. 2. As can be seen in FIG. 2, in addition to MOS capacitances C202 and C203, capacitance C204 exists at one signal terminal of capacitive circuit 101, while capacitance C205 exists at the other. If capacitive circuit 101 is used as a bypass capacitor with one end coupled to ground potential, the relatively small parasitic capacitances C204 and C205 are not significant. Capacitance C204 will simply add to the total bypass capacitance while capacitance C205 will be shorted out. However, in other circuit applications, significant signal loss can occur due to the capacitive path to ground provided by both parasitic capacitors C204 and C205.
Accordingly, it is desirable to provide a floating capacitive structure that can be manufactured using a conventional CMOS process and which minimizes performance problems due to parasitic capacitance.